18.10.2017

Recent Intel Scalable processors (Skylake) and next-generation Intel® CPUs feature large core counts, wide SIMD units (AVX-512) and high-bandwidth memory (e.g. on Intel Xeon Phi 7200 series - Knights Landing). Existing codes need to be modernized to take full advantage of the architectural features of these CPUs. Newly developed code should be designed to do so from the beginning.

We invite code developers to this 3-day workshop on advanced code optimization techniques on state-of-the-art and tomorrow`s multi- and many-core processors.

Agenda Survey

Your wishes for topics of the workshop are welcome - please submit your ideas using our Agenda Survey:

https://goo.gl/forms/bkCFXXWK1Yd6Zcce2


Registration

For more details and registration, please go to

https://par-prog-workshop-2017-zib.eventbrite.com
or
https://goo.gl/3vAJGY